Nowadays, the demands placed on embedded systems in terms of performance and energy requirements are constantly increasing. The demands on computing power are due to modern algorithms, especially in the field of machine learning, which are to be executed on even the smallest devices (edge AI). The energy requirements of such systems must nevertheless remain low so that they can be powered by batteries or energy-harvesting technologies at their place of use. Only modern processors with application-specific instruction set extensions and accelerators can meet such requirements. As part of this project, two instruction set extensions of the open processor architecture RISC-V were examined in more detail, which are potentially suitable for accelerating algorithms from various AI models. These are the vector extension and the extension for SIMD instructions. The aim of the project was to research and verify the current status of support for these extensions in simulators and compiler frameworks. Furthermore, software was to be created that can support developers in deciding whether an extension is suitable for a certain class of algorithms or not.

Objectives

The objectives of this project concern academic institutions and companies that want to create or customize application-specific RISC-V processors that use new instruction set extensions such as the vector or SIMD extensions. In this project, an overview of the support of new instruction set extensions in simulators and compilers for the RISC-V architecture should be researched. a group of representative benchmarks using algorithms relevant to modern embedded systems should be investigated using the vector and SIMD extensions. a toolchain should be created to automate the investigation of arbitrary programs with different simulator and compiler configurations and to simplify the evaluation of the results. While the research results relate specifically to the vector and SIMD extensions mentioned, the tools and benchmarks are also suitable for examining any other instruction set extensions.

Challenges

While the RISC-V specifications are public and managed by the RISC-V International Foundation, this does not apply to the processors or simulation models. Therefore, there are many different implementable cores, which have been created in different hardware description languages, as well as different simulators, which differ greatly in the support of the extensions as well as in the level of detail of the simulation. Support for modern instruction set extensions, such as vector extensions, is also available in the most widely used open compiler frameworks GCC and LLVM, but differs greatly in detail. In particular, the ability to deal with the flexible configurability of the vector extensions and also the capabilities for autovectorization were and are not yet fully developed in some cases. Finding combinations of compilers and simulators that support all the necessary features and deliver useful results that are suitable for performance analysis was a challenge, especially at the start of the project. Common libraries and benchmarks do not have code that is optimized for the vector and SIMD extensions of the RISC-V architecture, so autovectorized or hand-written code had to be used for the investigations.

Technology

As part of the project, a tool chain was developed that supports the automatic analysis of software using two compiler frameworks and currently two different RISC-V simulators. The specified programs are compiled and simulated with the instruction set extensions and the compiler settings, which can be selected by the user, and the generated simulation results are then processed and visualized. This gives the developer the opportunity to check with relatively little effort whether the use of one of the possible ISA extensions could prove useful or not. In preparation for the creation of the tools, the capabilities of the simulators and compilers with regard to the support of vector commands were also studied. Some aspects, in particular auto-vectorization, were examined in detail using special benchmarks. The results of these analyses also represent an important result of the project and are explained in the report. The toolchain was examined as part of the project using a selection of representative benchmarks. These include benchmarks from the embench suite, a collection of benchmark programs for embedded systems, as well as algorithms from the fields of machine learning as well as image and video processing.

Market

The information researched as part of the project and the programs created can help developers working with RISC-V processors to find or develop a suitable processor configuration for their application more quickly. As the programs are planned to be published on GitHub, they are available to any interested developer from academia or industry.

Consortium